ordering number : enn * 7051 12503as (ot) no. 7051-1/9 overview the LC35W256GM-70u and lc35w256gt-70u are 32768-words by 8-bit asynchronous silicon gate low supply voltage cmos srams. these devices adopt a full-cmos type six-transistor memory cell, and feature ultralow supply voltage operation, a low operating mode current drain, and an ultralow standby mode current drain. these device provide an oe pin for high-speed memory access and a ce chip select pin for device selection and low power mode control. thus these devices are optimal for use in systems that require low power and battery backup. they also allow easy expansion of memory capacities. their ultralow standby mode current drain allows them to be used in capacitor backed up systems. features ? supply voltage : 2.7v to 3.6v ? access time : 70 ns (max.) ? standby current : 2.0 a (ta 70c) : 5.0 a (ta 85c) ? operating temperature : C40c to +85c ? data retention voltage : 2.0 v to 3.6 v ? input levels : cmos-compatible [0.2 v cc /0.8 v cc ] ? sop28 (450mil) plastic package ? control input (oe, ce) ? common input/output pins, three-state outputs ? no clocks or timing signals required package dimensions unit: mm 3187b-sop28d 3221-tsop28a 0.15 18.0 14 15 28 1 (0.75) 1.27 0.4 8.4 11.8 1.0 (2.2) 0.1 2.5max preliminary sanyo: sop28d [LC35W256GM-70u] 13.4 11.8 22 28 1 7 8 21 0.05 0.5 (1.0) 8.0 0.2 0.125 1.2max (0.43) 0.55 sanyo: tsop28a [lc35w256gt-70u] LC35W256GM, gt-70u sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 256k (32768-words 8-bit) sram with oe and ce control pins cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircrafts control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein.
pin assignment no. 7051- 2 /9 LC35W256GM, gt-70u 28 v cc 27 we 26 a13 25 a8 24 a9 23 a11 22 oe 21 a10 20 ce 19 i/o8 18 i/o7 17 i/o6 16 i/o5 15 i/o4 a14 1 a12 2 a7 3 a6 4 a5 5 a4 6 a3 7 a2 8 a1 9 a0 10 i/o1 11 i/o2 12 i/o3 13 gnd 14 top view sop28 21 a10 20 ce 19 i/o8 18 i/o7 17 i/o6 16 i/o5 15 i/o4 14 gnd 13 i/o3 12 i/o2 11 i/o1 10 a0 9 a1 8 a2 oe 22 a11 23 a9 24 a8 25 a13 26 we 27 v cc 28 a14 1 a12 2 a7 3 a6 4 a5 5 a4 6 a3 7 top view tsop28
block diagram no. 7051- 3 /9 LC35W256GM, gt-70u i/o to 1 i/o8 a0 to a14 v cc gnd memory array data control data output data input control logic address input buffer decoder ce oe we pin name pin name pin function pin name pin function ce chip enable input v cc power oe output enable input gnd ground we write enable input i/o1 to i/o8 data inputs/outputs ao to a14 address inputs nc no conect truth table x: arbitrary h or l mode ce oe we i/o current read cycle l l h data output i cca write cycle l x l data input i cca output disable l h h high impedance i cca unselected h x x high impedance i ccs note * : the inputs may undershoot to C2.0v(min.)for periods less than 30ns. parameter symbol conditions ratings unit max supply voltage v cc max +4.6 v input voltage v in C0.3 * to v cc +0.3 v i/o voltage v i/o C0.3 to v cc +0.3 v operating temperature range topr C40 to +85 c storage temperature range tstg C55 to +125 c specifications absolute maximum ratings at ta = 25 c
no. 7051- 4 /9 LC35W256GM, gt-70u parameter symbol conditions ratings unit min typ max input/output capacitance c i/o v i/o = 0 v 6 10 pf input capacitance c in v in = 0 v 6 10 pf i/o capacitances at ta = 25 c, f = 1 mhz note * : this parameter is sampled and not 100% tested. parameter symbol conditions ratings unit min typ max supply voltage v cc 2.7 3.0 3.6 v input voltage v ih 0.8 v cc v cc + 0.3 v v il C0.3 * 0.2 v cc v recommended dc operating at ta = C40 c to +85 c, v cc = 2.7 v to 3.6 v note * : the inputs may undershoot to C2.0v(min.)for periods less than 30ns. parameter symbol conditions ratings unit min typ max input leakage current i li v in = 0 to v cc C1.0 +1.0 a i/o leakage current i lo v ce = v ih or v ce = v ih or C1.0 +1.0 a v we = v il , v i/o = 0 to v cc output high level voltage v oh1 i oh1 = C2.0 ma v cc C 0.4 v v oh2 i oh2 = C100 a v cc C 0.1 v output low level voltage v ol1 i ol1 = 2.0 ma 0.4 v v ol2 i ol2 = 100 a 0.1 v i cca2 v ce = v il , i i/o = 0 ma, v in = v ih or v il 1.2 ma operating current cmos input v ce = v il , i i/o = 0 ma, 70 ns cycle 20 25 ma i cca3 v in = v ih or v il , duty = 100% 100 ns cycle 15 18 ma 1 s cycle 1.5 2.5 ma v cc -0.2 v/0.2 v v ce 3 v cc C 0.2 v ta 25 c 0.01 a standby current input i ccs1 v in = 0 to v cc ta 70 c 2.0 a ta 85 c 5.0 a cmos input i ccs2 v ce = v ih , v in = 0 to v cc 0.4 ma dc characteristics at ta = C40 c to +85 c, v cc = 2.7 v to 3.6 v note * : reference value at v cc = 3.0 v, ta = +25 c
ac characteristics at ta = C40 c to +85 c, v cc = 2.7v to 3.6v ac test conditions input pulse level : v il = 0.2 v cc , v ih = 0.8 v cc input rise and fall time : 5 ns input and output timing reference levels : 0.5 v cc output load : 30 pf (including scope and jig) read cycle no. 7051- 5 /9 LC35W256GM, gt-70u parameter symbol LC35W256GM, gt-70u unit min max read cycle time trc 70 ns address access time taa 70 ns ce access time tca 70 ns oe access time toa 35 ns output hold time toh 10 ns ce output enable time tcoe 10 ns oe output enable time tooe 5 ns ce output disable time tcod 30 ns oe output disable time tood 25 ns write cycle parameter symbol LC35W256GM, gt-70u unit min max write cycle time twc 70 ns address setup time tas 0 ns write pulse width twp 50 ns ce setup time tcw 60 ns write recovery time twr 0 ns ce recovery time twr1 0 ns data setup time tds 40 ns data hold time tdh 0 ns ce data hold time tdh1 0 ns we output enable time twoe 5 ns we output disable time twod 30 ns
timing waveform read cycle note[1] no. 7051- 6 /9 LC35W256GM, gt-70u a0 to a14 ce oe dout1 to 8 data in stable note[5] write cycle [we write] note[6] a0 to a14 we ce dout1 to 8 note[7] note[5] din1 to 8 note[2] data in stable note[2] tcoe tooe toa tca toh taa tcod tood trc twp note[3] tas twc twod tcw1 note[4] two e twr tdh tds : invalid data : h or l
write cycle2 (ce write) note[6] notes: (1) in read cycle, we should be high. (2) during this period, i/o pins are in the output state, therefore the input signals of opposite phase to the outputs must not be applied. (3) the internal write time of the memory is defined by the overlap of ce low and we low. twp is measured from the falling edge of we to the earlier rising edge of ce or we. (4) the internal write time of the memory is defined by the overlap of ce low and we low. tcw is measured from the falling edge of ce to the earlier rising edge of ce or we. (5) if one of these conditions[oe is high, ce is high, we is low] at least is satisfied, dout goes to high impedance state. (6) in write cycle, oe =v ih or v il . (7) dout is in the same phase of written data of this cycle. ? functional operation of the device at any conditions beyond absolute maximum ratings is not implied. ? cmos-lsi input pins must be high or low to prevent them from floating or the level which neither v ih nor v il . no. 7051- 7 /9 LC35W256GM, gt-70u write cycle2(ce write) note[6] a0 to a14 we ce hi-z hi-z dout1 to 8 note[5] dout1 to 8 note[2] data in stable note[2] twp note[3] tas twc tcw note[4] twr1 tdh1 tds : invalid data : h or l
circuit design notes when designing an actual application circuit, consider each of the following aspects and assure that none of the maximum ratings are ever exceeded. ? supply voltage fluctuations ? sample-to-sample variations in electrical characteristics of the electrical components used, including semiconductor devices, resistors, and capacitors. ? the ambient temperature ? fluctuations in the input and clock signals ? possible application of abnormal pulses also, these ics must be operated within the allowable operating ranges. if any of the input pins on this cmos ic are left open, intermediate potentials may be generated leading to incorrect operation due to through currents or other phenomenon. unused input pins must be handled as stipulated. no. 7051- 8 /9 LC35W256GM, gt-70u data retention waveform [1] v cc vccl * v ih v dr v ce gnd vccl * 2. 7v tr data retention mode tcdr v ce 3 vcc 0.2v parameter symbol conditions ratings unit min typ max data retention power supply voltage v dr v ce 3 v cc C 0.2 v 2.0 3.6 v ta 85 c 2.0 a data retention current i ccdr v cc = 3 v, v ce 3 v cc C 0.2 v ta 70 c 1.5 a ta 25 c 0.01 a chip enable setup time tcdr 0 ns chip enable hold time tr trc * ns data retention characteristics at ta = C40 c to +85 c note * : read cycle time
ps no. 7051- 9 /9 LC35W256GM, gt-70u this catalog provides information as of january, 2003. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customers products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customers products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the delivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
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